The present invention relates generally to semiconductor device processing techniques, and, more particularly, to a method and structure to improve thermal dissipation from semiconductor devices.
In semiconductor manufacturing, a fabricated integrated circuit (IC) device is typically assembled into a package or module to be utilized on a printed circuit board as part of a larger circuit. In order for the leads of the package or module to make electrical contact with the bonding pads of the fabricated IC device, a metal bond is formed to make a connection between the bonding pad of the IC device and a lead extending to the package lead frame. In other configurations, such as a controlled collapse chip connection (C4), a solder ball connection is made between the IC device and the ceramic or polymeric chip carrier.
As heat is generated during the functioning of integrated circuit chips (ICs), the thermal resistance to the heat sink must be small so that the operating temperature of the chip is low enough to assure the continued reliable operation of the device. The problem of heat removal becomes more difficult as chip geometries are scaled down and operating speeds are increased, resulting in increased power density. The ability to adequately cool the chips can therefore be a limiting factor in the further increase of system performance. Integrated circuit chips mounted wiring face down on wiring substrates, and particularly multiple chips on a common substrate such as is found in a multichip module (MCM), present special cooling difficulties. In an MCM, the chips may be mounted very close together and nearly cover an entire top surface of the MCM wiring substrate.
Additionally, the chips may have different cooling requirements. For example, a processor chip may have a higher power density (W/cm2) than a memory chip mounted on the same wiring substrate, or first level package. Further, the maximum allowed device junction temperature may be different for different chips mounted to the same wiring substrate. An additional problem is that processor chips, and other chips, frequently have a “hot spot” which can have a heat flux (W/cm2) significantly greater than the average heat flux across the entire chip, resulting in temperatures approximately 20° C. hotter than the average chip temperature in these localized regions. A thermal solution which may be adequate for the average chip power density may not be adequate to allow reliable operation of the hot spot region of the chip.
Materials are chosen in the module assemblies which maximize the thermal conductivity from the device to an appropriate heat sink. A common technique for reducing the thermal resistance from a high-power IC to a heat sink, or cooling plate, is to add an intermediate layer of a thermally conductive material between the chip and the heat sink, or cooling plate. Due to the difference in thermal expansion between the chip and the material of the cooling plate or heat sink, which is typically copper or aluminum, a compliant thermally conductive material is required. The addition of a heat spreader can be advantageous because the compliant thermally conductive material layer is usually a significant fraction of the total thermal resistance.
Current high end packaging technology utilizes a thermal paste compound to couple a back side of the semiconductor device to the heat sink, which may include a copper hat, for example. Control over the thickness of this thermal paste is critical to the efficiency of the thermal transfer between the semiconductor device and the copper hat.
Typically, an elaborate system of semi-free soldered pistons is employed to register to the exact device height position of each individual device to control the thermal paste gap. The pistons are precisely positioned within the heat sink or hat to precisely match the position of the backsides of each individual device, and then soldered into place. As a result, an appropriate thickness shim can be used to set a controlled thermal paste gap on all devices on the module assembly.
This process, while being inherently expensive due to process step complexity and hat/piston hardware cost, is also prone to chip height registration errors and variations, due to for example, stuck pistons which do not move freely during solder reflow, and thus, is not entirely reliable. Additional variation and non-uniformity of thermal paste gaps can be induced by chip tilt and warpage. While not as much a concern on ceramic packaging, warpage can become significant on organic substrates due to a difference in coefficients of thermal expansion (ΔCTE) between the chip and the chip carrier substrate and especially the more flexible nature of the organic chip carrier substrate. Finally, on low and mid-range multiple chip packages, on which the above described hat/piston technology is cost prohibitive, chip thickness variations directly result in variation in the thermal paste gap.